1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device and a method of manufacturing the same in which resistance of a wiring layer having a large area is not increased.
2. Description of the Related Art
As the size of wiring formations decrease, there is a tendency for the wiring intervals to become narrower, the wiring capacitance to increase, and the operating speed of the circuit to decrease. In order to prevent such a tendency, various kinds of interlayer films of low dielectric constant have been proposed. In FIG. 10, a related art which uses HSQ (Hydrogen Silsesquioxane) as an interlayer insulating film is shown. As shown in FIG. 10, a first oxide film 102 is formed on a substrate (not shown) and a first wiring layer 101 is formed on the oxide film 102. A liner oxide film 106, a HSQ film 107 and a plasma oxide film 108 are formed over the first wiring layer 101 together form an interlayer insulator. A second wiring layer 113 on the oxide film 108 is connected to the first wiring layer 101 by a tungsten plug 112, which is formed in a via hole 109. According to this related art, the HSQ film in the interlayer insulator, prevents the wiring resistance from increasing.
However, in this related art, a cavity 100 forms in the sides of via hole 109 when etching through the interlayer insulator. The HSQ 107 is horizontally etched so that the sides of via hole 109 bow outwardly. In this event, via hole 109 is not completely filled with tungsten, leaving cavity 100 around the tungsten plug 112. As a result, the absence of HSQ around the via hole causes the resistance to increase.
Specifically, when the wiring layers cover a large area, the sides of the via hole are more easily swelled into the bow shape. The reason is that an application film, such as HSQ, is easily formed in a thick layer on the wiring layer having a large area. In order to perfectly bore the via hole in the interlayer insulator that includes the thick HSQ film, the etching is carried out so that the bottom of the via hole 109 exposes the underlying wiring layer 101, once the wiring layer 101 is exposed, the etching does not progress downwardly, but progresses horizontally in the HSQ film 107. When the etching rate of the HSQ is higher than that of any of the layers, the bowing of the sides of the via hole 109 occurs.
Thus, it is desirable to prevent the horizontal spreading of the via hole in order to prevent the resistance from increasing.
Therefore, the object of the present invention is to solve the above problem.
In order to accomplish this object, according to a first aspect of the present invention, there is provided a semiconductor device comprising a first wiring layer, an insulating layer over the first wiring layer, a second wiring layer on the insulating layer, a first hole formed in the first wiring layer, a second hole formed in the insulating layer connecting with at least a part of the first hole, and a conductive material in the first and second holes that electrically connects the first wiring layer to the second wiring layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising, forming a first wiring layer, forming a first hole in the first wiring layer, forming an insulating layer on the wiring layer and in the first hole, forming a second hole in the insulating layer, the second hole exposing at least a part of an inner side surface of the first hole, and filling the second hole with a conductive material.
According to a third aspect of the present invention, there is provided a method of avoiding of over-etching of an insulator layer, comprising, forming a first horizontal wiring layer, forming a first hole in the first wiring layer, forming an insulating layer on the wiring layer and in the first hole, etching a second hole in the insulating layer, the second hole exposing at least a part of an inner side surface of the first hole, the first hole having a depth that avoids horizontal over-etching of the insulating layer above the first hole when forming the second hole, and filling the second hole with a conductive material.
According to the present invention, the second hole is preventing from horizontally swelling. Therefore, a resistance of the wiring layer does not increase.